1. Field of the Invention
The present invention relates to an integrated circuit and a method for manufacturing an integrated circuit on a semiconductor chip.
2. Description of the Background Art
In semiconductor technologies there are provided vertical bipolar transistors with various dielectric strengths and frequency capabilities. In this regard, dielectric strength generally increases with decreasing collector doping. Relatively low collector doping likewise results in a relatively low cutoff frequency.
A method of selective collector implantation is known, especially for the high frequency range. In this context, a first and a second collector region are created from a uniform collector epitaxy; a collector of a first bipolar transistor with high dielectric strength and low frequency capability is produced from the first collector region, and a collector of a second bipolar transistor with lower dielectric strength and better frequency capability is produced from the second collector region. To this end, the second collector region is provided with an additional collector implantation (SIC—selectively implanted collector) in a limited area. As a result of this selective collector implantation, the dopant concentration in the second collector region is raised above the dopant concentration in the first collector region.
In semiconductors, pn junctions exist, in particular, as “long” or “short” diodes. In a “long” p-n-n+ diode, the space charge zone ends on the n-side in the n− region for reverse voltages such as are present at the pn junction under normal operating conditions, whereas in “short” diodes, the space charge zone reaches through into the n+ region. As a result of the reach-through, the blocking capability of “short” diodes is reduced as compared to the blocking capability of a “long” diode with the same dopant level. For a bipolar transistor with a given collector-base breakdown voltage, a certain extension of the collector drift zone is thus necessary, and consequently requires a certain thickness of the collector epitaxy.
Conversely, the collector resistance is an important criterion for the quality of the bipolar transistor, especially in the high frequency range. One part of the collector resistance is the resistance of a portion of the collector drift zone that may not be depleted under normal operating conditions. In general, the extension of the collector space charge zone is reduced under the desired operating conditions by a sufficiently high selective collector implantation. Since it is also necessary in setting the thickness of the collector epitaxy to consider the needs of the higher blocking transistor, the second collector region frequently is not fully depleted in operation of the second bipolar transistor. This disadvantageously increases the collector resistance of the second bipolar transistor. For example, a 120 nm non-depleted collector drift zone with a typical cross-section of 20×0.6 μm2 still leads to an additional collector resistance of 8 ohms, even at the high collector doping of 1e17 cm−3; in many cases this constitutes the major portion of the overall collector resistance.
In the high frequency range, the transistors are preferably operated at high current densities to reduce the charge transfer times of the diffusion capacitance layers. In this connection, the space charge density resulting from the ion cores (p-charged, in the case of an npn transistor) in the depleted part of the collector drift zone is at least partially compensated by the space charge density of the electrons moving at terminal velocity through the space charge zone. The collector edge of the space charge zone thus migrates toward the subcollector. At the operating point optimal for fT, essentially only the subcollector edge contributes to the collector resistance, while the collector drift zone does not.
In producing the aforementioned collector drift zones according to the conventional art, a silicon collector epitaxy approximately 190 nm thick and doped at 1e17 cm−3 is grown on a highly n-doped monocrystalline silicon layer as a subcollector, wherein a thickness margin of 20 nm serves to compensate for the diffusion of dopant out of the highly n-doped silicon layer. This epitaxial layer “as grown” constitutes the low-doped collector drift zone.